Semiconductor device with a metal line and method of forming the same

ABSTRACT

A method of forming a metal line in a semiconductor device including forming a first insulation layer and a first etch stop layer on a conductive layer, and forming a first photosensitive layer pattern on the first etch stop layer; forming a first opening by etching the first etch stop layer; forming a second insulation layer and a second etch stop layer on the first insulation layer and the first etch stop layer, and forming a second photosensitive layer pattern on the second etch stop layer; forming a second opening by etching the second etch stop layer; simultaneously forming an inter-connection groove and a via hole by etching the first insulation layer and the second insulation layer using the second etch stop layer and the first etch stop layer as a mask; and forming a metal line by filling the inter-connection groove and the via hole with conductive materials.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to and the benefit of Korean PatentApplication No. 10-2004-0106940 filed in the Korean IntellectualProperty Office on Dec. 16, 2004, the entire contents of which areincorporated herein by reference.

BACKGROUND OF THE INVENTION

(a) Field of the Invention

The present invention relates to a semiconductor device with a metalline and a method of forming the same. More particularly, the presentinvention relates to a metal line in a semiconductor device and a methodof forming the same by using a low-k (low dielectric constant)insulation layer.

(b) Description of the Related Art

As semiconductor devices have become highly integrated, logic devicesare also required to have higher speed and higher integration. In orderto enhance integration of a semiconductor device, metal lines thereinare required to be miniaturized.

However, a higher speed of a semiconductor device is not easily achieveddue to line delay.

An aluminum alloy is conventionally used as a wiring material in LSI(Large Scale Integration), but copper (Cu) has recently been used as awiring material in LSI because copper has low resistivity and highstrength against EM (electro-migration).

However, since copper is hard to etch and since it can be oxidizedduring manufacturing processes, a damascene process has recently beenused for forming a copper line.

A damascene process is performed by the following steps; firstly, aninter-connection groove in which an upper wire will be formed is formedon an insulation layer, and a via hole connecting the upper wire with alower wire or substrate is also formed on an insulation layer; andsecondly, a metal line is formed by performing a CMP (ChemicalMechanical Polishing) process for copper which is filled in theinter-connection groove and via hole.

A low-k (low dielectric constant) insulation layer is used with a copperline in such a damascene process, because it may increase the speed of adevice by reducing a parasitic capacitance between metal lines andreduce cross-talk of a device.

Hereinafter, a conventional method of forming a metal line in asemiconductor device using a dual damascene process will be describedwith reference to FIG. 1A to FIG. 1F.

FIG. 1A to FIG. 1F are cross-sectional views showing sequential statesof a method of forming a metal line in a semiconductor device using adual damascene process.

Referring to FIG. 1A, a lower conductive layer 110, an etch stop layer120, a lower insulation layer 130, and an upper insulation layer 140 aresequentially formed.

Referring to FIG. 1B, a photosensitive layer pattern 150 having anopening D1-1 for a via hole is formed on the upper insulation layer 140.

However, when a lithography process is performed for the photosensitivelayer pattern 150, a photoresist tail (not shown) may be createdthereon. A photoresist tail may occur when a via hole is miniaturizeddue to miniaturization of a metal line, when a depth of a via hole to beetched is increased, and when a thickness of a photosensitive layer usedas an etching barrier is also increased.

As shown in FIG. 1C, a via hole is formed up to the etch stop layer 120by selectively etching the upper insulation layer 140 and lowerinsulation layer 130 while using the photosensitive layer pattern 150 asan etch mask. Thereafter, the photosensitive layer pattern 150 isremoved by performing an ashing process.

Referring to FIG. 1D, a photosensitive layer 160 is deposited on theentire surface of the upper insulation layer 140 including the via hole,and the photosensitive layer 160 is left only in the via hole byperforming blanket etching. When subsequent processes for forming aninter-connection groove are performed, the photosensitive layer 160remaining in the via hole is used as a barrier layer for preventingremoval of or damage to the etch stop layer 120 below the via hole.

Subsequently, a photosensitive layer pattern 170 having an opening isformed on the upper insulation layer 140. The opening has the same widthas a predetermined width D1-2 of an inter-connection groove. Thereafter,the upper insulation layer 140 is etched in the predetermined thicknessof a metal line by using the photosensitive layer pattern 170 as an etchmask.

Referring to FIG. 1E, the photosensitive layer pattern 170 andphotosensitive layer 160 are removed by an ashing process, and the lowerconductive layer 110 is exposed by removing the etch stop layer 120below the via hole through blanket etching.

According to a conventional method of forming a metal line in asemiconductor device, when the lower insulation layer 130 and the upperinsulation layer 140 are formed as low-k (low dielectric constant)insulation layers including an organic polymer, they are damaged byoxygen plasma that is used in two ashing processes for thephotosensitive layer patterns 150 and 170.

More particularly, when the lithography process for the photosensitivelayer pattern 170 having the same width as an inter-connection groove isnot performed properly, a rework process for removing the photosensitivelayer pattern should be performed. However, during the rework process,the insulation layers 130 and 140 having an organic polymer are severelydamaged because they are already exposed at both sidewalls of theinter-connection groove and the via hole.

Thereafter, as shown in FIG. 1F, a barrier metal layer 180 is formed inthe inter-connection groove and the via hole, and a metal line isfinally formed by polishing conductive materials filling theinter-connection groove and the via hole through a CMP process.

Such a conventional dual damascene process for forming a metal line mayinduce a photoresist tail, and it may induce severe damage to aninsulation layer during ashing and re-ashing processes.

The above information disclosed in this Background section is only forenhancement of understanding of the background of the invention andtherefore it may contain information that does not form the prior artthat is already known in this country to a person of ordinary skill inthe art.

SUMMARY OF THE INVENTION

The present invention has been made in an effort to provide asemiconductor device with a metal line and a method of forming the samehaving advantages of using an improved dual damascene process.

An exemplary semiconductor device with a metal line according to anembodiment of the present invention includes: a conductive layer; afirst insulation layer that is formed on the conductive layer and has afirst opening; an etch stop layer that is formed on the first insulationlayer and has a second opening, and protects the first insulation layerfrom etching; a second insulation layer that is formed on the etch stoplayer and has the second opening; a via hole that is connected with theconductive layer and is formed in the first opening; and a metal linethat is formed by filling the inter-connection groove and via hole withconductive materials, and that is electrically connected to theconductive layer. The first insulation layer can additionally include athird opening that can be connected to a lower part of the firstopening, and composes the via hole with the first opening, and that hasa smaller width than the first opening.

The first insulation layer or the second insulation layer having thelow-k (low dielectric constant) can be composed of one among a Si—Obased inorganic polymer, a carbon-based organic polymer, afluorine-doped oxide layer, or a carbon-doped oxide layer.

The organic polymer can be composed of at least one among a polyallyether resin, a cyclic fluorine resin, a siloxane copolymer, a fluoropolyally ether resin, a poly pentafluoride styrene resin, a polytetrafluoride styrene resin, a fluoro polyimide resin, a fluoro polynaphthalene resin, a polycide resin, etc.

The etch stop layer can be formed at a thickness of 5 to 30 nm, and theconductive materials can simultaneously fill in the inter-connectiongroove and via hole by using a CMP process.

An exemplary method of forming a metal line in a semiconductor deviceincludes: forming a first insulation layer and first etch stop layer ona conductive layer, and forming a first photosensitive layer pattern onthe first etch stop layer; forming a first opening for a via hole byetching the first etch stop layer using the first photosensitive layerpattern as a mask; forming a second insulation layer and second etchstop layer on the first insulation layer and first etch stop layer, andforming a second photosensitive layer pattern on the second etch stoplayer; forming a second opening for an inter-connection groove byetching the second etch stop layer using the second photosensitive layerpattern as a mask; forming the inter-connection groove and via hole byetching the first insulation layer and second insulation layer using thesecond etch stop layer and first etch stop layer as a mask; and forminga metal line by filling the inter-connection groove and via hole withconductive materials.

Another exemplary method of forming a metal line in a semiconductordevice includes: sequentially forming a first etch stop layer, a firstinsulation layer, and a second etch stop layer on a conductive layer;forming a first photosensitive layer pattern having a first opening onthe second etch stop layer; etching the second etch stop layer by usingthe first photosensitive layer pattern as a mask to a degree that thefirst insulation layer is exposed, and then removing the firstphotosensitive layer pattern; sequentially forming a second insulationlayer and a third etch stop layer on the first insulation layer andsecond etch stop layer, and forming a second photosensitive layerpattern having a second opening on the third etch stop layer; etchingthe third etch stop layer by using the second photosensitive layerpattern as a mask to a degree that the second insulation layer isexposed, and removing the second photosensitive layer pattern; formingan inter-connection groove and a via hole by sequentially etching thefirst insulation layer using the third etch stop layer and the secondetch stop layer as a mask; forming a spacer insulation layer on theentire surface of a substrate including the inter-connection groove andthe via hole; forming a spacer at both sidewalls of the inter-connectiongroove and the via hole by performing an etch back process using thethickness of the spacer insulation layer as a target; forming a via holeby additionally etching the first insulation layer to a degree that thefirst etch stop layer is exposed; simultaneously forming theinter-connection groove and via hole by removing the first etch stoplayer, the second etch stop layer, the third etch stop layer, and thespacer insulation layer; and forming a metal line by performing a CMPprocess for polishing conductive materials which fill in theinter-connection groove and the via hole.

The first insulation layer or the second insulation layer having thelow-k (low dielectric constant) can be composed of one among a Si—Obased inorganic polymer, a carbon-based organic polymer, afluorine-doped oxide layer, or a carbon-doped oxide layer.

During the forming of the first photosensitive layer pattern and secondphotosensitive layer pattern, the first insulation layer and the secondinsulation layer can be protected by the second etch stop layer and thethird etch stop layer in a rework process to remove the firstphotosensitive layer pattern or the second photosensitive layer patternfor performing an additional lithography process.

The inter-connection groove and the via hole can be simultaneouslyformed by performing etching with the use of the third etch stop layerpattern as a mask.

The inter-connection groove and the via hole having a finer size than asize limit obtained by a lithography process can be formed by adjustinga thickness of the spacer.

Before the conductive materials fill in the inter-connection groove andthe via hole, a barrier metal layer can be formed at both sidewallsthereof, and the barrier metal layer may be composed of at least oneamong Ta, TaN, TiN, WN, TaC, WC, TiSiN, or TaSiN.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A to FIG. 1F are cross-sectional views showing sequential statesof a conventional method of forming a metal line in a semiconductordevice using a dual damascene process.

FIG. 2 is a cross-sectional view showing a semiconductor device having ametal line formed by a first exemplary embodiment of the presentinvention.

FIG. 3A to 3K are cross-sectional views showing sequential stages of amethod of forming a metal line in a semiconductor device according to asecond exemplary embodiment of the present invention.

DETAILED DESCRIPTION OF THE EMBODIMENTS

An exemplary embodiment of the present invention will hereinafter bedescribed in detail with reference to the accompanying drawings.

In the following detailed description, only certain exemplaryembodiments of the present invention have been shown and described,simply by way of illustration. As those skilled in the art wouldrealize, the described embodiments may be modified in various differentways, all without departing from the spirit or scope of the presentinvention.

To clarify multiple layers and regions, the thicknesses of the layersare enlarged in the drawings. Like reference numerals designate likeelements throughout the specification. When it is said that any part,such as a layer, film, area, or plate, is positioned on another part, itmeans the part is directly on the other part or above the other partwith at least one intermediate part. On the other hand, if any part issaid to be positioned directly on another part it means that there is nointermediate part between the two parts.

Hereinafter, a semiconductor device having a metal line formed by afirst exemplary embodiment of the present invention will be describedwith reference to FIG. 2.

FIG. 2 is a cross-sectional view showing a semiconductor device having ametal line formed by a first exemplary embodiment of the presentinvention.

As shown in FIG. 2, according to a first exemplary embodiment of thepresent invention, a lower conductive layer 210, a lower etch stop layer220 having an opening for a via hole, a lower insulation layer 230having an opening for a via hole, an upper etch stop layer 240 having anopening for an inter-connection groove, and an upper insulation layer260 having an opening for an inter-connection groove are formed on asemiconductor device including a via hole and a metal line.Subsequently, the via hole and inter-connection groove are filled with aconductive material.

The lower conductive layer 210 is formed of a conductive material, andit can be a semiconductor substrate or a lower metal line in amulti-layered structure. Here, the upper etch stop layer 240 is formedwith a relatively small thickness, preferably 5 to 30 nm.

The lower insulation layer 230 is formed as a low-k (low dielectricconstant) insulation layer, and the low-k insulation layer is notspecifically limited in the first exemplary embodiment of the presentinvention. That is, a preferable low-k insulation layer includes a Si—Obased inorganic polymer, a carbon-based organic polymer, afluorine-doped oxide layer, or a carbon-doped oxide layer. The organicpolymer can include a polyally ether resin, a cyclic fluorine resin, asiloxane copolymer, a fluoro polyally ether resin, a poly pentafluoridestyrene resin, a poly tetrafluoride styrene resin, a fluoro polyimideresin, a fluoro poly naphthalene resin, a polycide resin, etc.

The lower insulation layer 230 can be formed by using one among a PECVD(Plasma Enhanced CVD), HDP-CVD (High Density Plasma CVD), APCVD(Atmospheric Pressure CVD), or spin coating scheme.

The conductive material can be composed of at least one among aluminum(Al), an aluminum alloy (Al-alloy), copper (Cu), gold (Au), silver (Ag),tungsten (W), and molybdenum (Mo).

Hereinafter, a method of forming a metal line in a semiconductor deviceaccording to a second exemplary embodiment of the present invention willbe described with reference to FIG. 3A to FIG. 3K.

FIG. 3A to FIG. 3K are cross-sectional views showing sequential stagesof a method of forming a metal line in a semiconductor device accordingto the second exemplary embodiment of the present invention.

As shown in FIG. 3A, a lower etch stop layer 220, a lower insulationlayer 230, and an upper etch stop layer 240 are sequentially formed on alower conductive layer 210.

Referring to FIG. 3B, a photosensitive layer pattern 250 having anopening D2-1 for forming a via hole is formed on the upper etch stoplayer 240. Here, the opening D2-1 is formed more widely than an actualopening for a via hole.

The photosensitive layer pattern 250 is used as an etch mask whenetching the upper etch stop layer 240. Since the upper etch stop layer240 is formed to a small thickness as described above, and the openingof the photosensitive layer pattern 250 is formed more widely than anactual opening for a via hole, an etching process can be easilyperformed and a photoresist tail, which can otherwise be created after alithography process, can be prevented. More specifically, if the upperetch stop layer 240 is formed to a large thickness, a photoresist tailcan be created due to strict etching conditions, such as a long etchingtime. However, according to the second exemplary embodiment of thepresent invention, since the upper etch stop layer 240 is formed to asmall thickness, a photoresist tail can be prevented because strictetching conditions are not required. In addition, the opening D2-1 canbe adjusted as necessary. More specifically, the opening D2-1 can beappropriately adjusted according to the thickness of a spacer which isformed in the subsequent process.

Referring to FIG. 3C, the upper etch stop layer 240 is etched to adegree that the lower insulation layer 230 is exposed by using thephotosensitive layer pattern 250 as an etch mask, and then thephotosensitive layer pattern 250 is removed by an ashing process. Anashing method for the photosensitive layer pattern 250 is notspecifically limited in the second exemplary embodiment of the presentinvention, but an oxygen plasma ashing method can be used therein.

As shown in FIG. 3D, an upper insulation layer 260 and a hard mask layer270 are sequentially formed on the lower insulation layer 230 and theupper etch stop layer 240, and then a photosensitive layer pattern 280having an opening D2-2 is formed on the hard mask layer 270. Here, theopening D2-2 can be formed more widely than a predeterminedinter-connection groove, and the hard mask layer 270 is formed at a verysmall thickness.

Since the hard mask layer 270, which is etched by using thephotosensitive layer pattern 280 as a mask, is formed to a very smallthickness, and the opening D2-2 is formed more widely than apredetermined inter-connection groove, a photoresist tail cannot occurafter a lithography process.

According to the conventional method of performing a dual damasceneprocess, the opening D2-1 or D2-2 has the same width as the via hole andthe inter-connection groove. However, according to the second exemplaryembodiment of the present invention, a photosensitive layer patternhaving a wider width than the via hole and inter-connection groove isformed, and then a process for adjusting the width of the via hole andthe inter-connection groove is subsequently performed. Consequently, avia hole and an inter-connection groove having a fine width which cannotbe obtained by a lithography process can be formed. Hereinafter, theprocess for adjusting the width of the via hole and the inter-connectiongroove will be described in detail.

The upper insulation layer 260, like the lower insulation layer 230, isformed as a low-k insulation layer, and it is composed of the samematerial as that of the lower insulation layer 230.

According to the second exemplary embodiment of the present invention,the upper insulation layer 260 and the lower insulation layer 230 areformed to a thickness large enough for the via hole and inter-connectiongroove to be formed therein.

According to the second exemplary embodiment of the present invention,the lower insulation layer 230 is protected by the upper etch stop layer240 that is formed thereon, and the upper insulation layer 260 isprotected by the hard mask layer 270 that is formed thereon. Morespecifically, during the ashing process for removing the photosensitivelayer patterns 250 and 280, the lower insulation layer 230 and the upperinsulation layer 260 are respectively protected by the upper etch stoplayer 240 and the hard mask layer 270.

Here, even if portions of the lower insulation layer 230 and upperinsulation layer 260 exposed by the opening D2-1 and D2-2 may be damagedby the ashing process, there are no negative effects for metal lines ofa semiconductor device because the exposed portions are finally removedby the subsequent process.

More particularly, when the lithography process for the photosensitivelayer pattern 250 and 280 is not properly performed, the rework processfor removing the photosensitive layer pattern needs to be performed inorder to perform the lithography process again. During the reworkprocess, the upper etch stop layer 240 and the hard mask layer 270protect the insulation layers 230 and 260. Therefore, the insulationlayers 230 and 260 composed of an organic polymer cannot be damaged inthe rework process.

Here, the hard mask layer 270, the upper etch stop layer 240, and thelower etch stop layer 220 need to be composed of materials having astrong tolerance for an etching process performed for forming metallines of a semiconductor device, and according to the second exemplaryembodiment of the present invention, they can be composed of siliconnitride.

Referring to FIG. 3E, the hard mask layer 270 is etched by using thephotosensitive layer pattern 280 as a mask to a degree that the upperinsulation layer 260 is exposed.

As shown in FIG. 3F, the inter-connection groove and a portion of thevia hole are simultaneously formed by sequentially etching the upperinsulation layer 260 and a portion of the lower insulation layer 230using the hard mask layer 270 and the upper etch stop layer 240 as amask.

Here, the etching of the lower insulation layer 230 is partiallyperformed up to a portion thereof or is completely performed to a degreethat the lower etch stop layer 220 is exposed.

As shown in FIG. 3G, a spacer insulation layer 290 is formed on theentire surface of the substrate including the inter-connection grooveand the via hole.

The spacer insulation layer 290 is composed of a material having thesame etch rate as the hard mask layer 270, the upper etch stop layer240, and the lower etch stop layer 220. According to the secondexemplary embodiment of the present invention, the spacer insulationlayer 290 is composed of silicon nitride.

Since the widths of the inter-connection groove and the via hole aredetermined by the width of the lower part of the spacer, they areadjusted by controlling the forming thickness of the spacer insulationlayer 290.

Therefore, the inter-connection groove and via hole having a finer sizethan a size limit obtainable by a lithography process can be formed byadjusting the forming thickness of the spacer insulation layer 290.

As shown in FIG. 3H, a spacer is formed at both sidewalls of theinter-connection groove and the via hole by performing an etch backprocess without a mask, using the thickness of the spacer insulationlayer 290 as a target.

As shown in FIG. 3I, the final via hole having an opening D2-11 isformed by additionally etching the lower insulation layer 230 to adegree that the lower etch stop layer 220 is exposed.

Therefore, a via hole having a deep and fine opening can be formed inthe semiconductor device by such a two step method.

Consequently, according to the second exemplary embodiment of thepresent invention, a part of the lower conductive layer 210 connectedwith the via hole, namely the thickness of the metal line, can be formedto a small thickness.

As shown in FIG. 3J, a damascene pattern composed of theinter-connection groove and via hole is finally formed by simultaneouslyremoving the hard mask layer 270, the spacer insulation layer 290, theupper etch stop layer 240, and the lower etch stop layer 220 at thelower part of the via hole.

Here, according to the second exemplary embodiment of the presentinvention, since the hard mask layer 270, the spacer insulation layer290, the upper etch stop layer 240, and the lower etch stop layer 220are formed by using materials having the same etch selectivity, they canbe removed simultaneously. In more detail, the hard mask layer 270, thespacer insulation layer 290, the upper etch stop layer 240, and thelower etch stop layer 220 are composed of silicon nitride, and they aresimultaneously removed by dry etching or wet etching.

As shown in FIG. 3K, a metal line 292 is formed by polishing conductivematerials filling the inter-connection groove and the via hole through aCMP process.

A metal line can be formed by using one among a method of reflowing aconductive layer which is formed by a sputter scheme, a CVD (ChemicalVapor Deposition) method, and an electroplating method.

When the electroplating method is used for forming a metal line, a seedlayer can be formed in order to allow an electric current to flow duringan electrolytic process.

In addition, a barrier metal layer 291 can be formed before conductivematerials fill the inter-connection groove and the via hole. When ametal line is formed by a damascene process using copper (Cu), aninsulation characteristic of an interlayer insulation layer can bedegraded by diffusion of a copper conductive material. The barrier metallayer 291 prevents such degradation.

The barrier metal layer can be composed of at least one among Ta, TaN,TiN, WN, TaC, WC, TiSiN, or TaSiN, and it is formed by using one amongPVD (Physical Vapor Deposition), CVD (Chemical Vapor Deposition), or ALD(Atomic Layer Deposition) schemes.

The exemplary embodiment of the present invention provides a method offorming a metal line in a semiconductor device in which damage to aninsulation layer can be prevented.

In addition, since an inter-connection groove and a via hole having afiner size than a size limit obtained by the lithography process can beformed using a spacer, the reliability and yield of semiconductordevices can be enhanced.

While this invention has been described in connection with what ispresently considered to be practical exemplary embodiments, it is to beunderstood that the invention is not limited to the disclosedembodiments, but, on the contrary, is intended to cover variousmodifications and equivalent arrangements included within the spirit andscope of the appended claims.

1. A semiconductor device with a metal line, said semiconductor devicecomprising: a conductive layer; a first insulation layer formed on theconductive layer and having a first opening; an etch stop layer formedon the first insulation layer, having a second opening, and protectingthe first insulation layer from etching; a second insulation layerformed on the etch stop layer and having the second opening; a via holeconnected with the conductive layer, and formed in the first opening; aninter-connection groove connected with the via hole, and formed on thesecond opening; and a metal line formed by filling the inter-connectiongroove and the via hole with conductive materials, and electricallyconnected to the conductive layer.
 2. The semiconductor device of claim1, wherein the first insulation layer further includes a third openingconnected to a lower part of the first opening, and composes the viahole with the first opening, and has a smaller width than the firstopening.
 3. The semiconductor device of claim 1, wherein the firstinsulation layer or the second insulation layer has a low-k (lowdielectric constant).
 4. The semiconductor device of claim 3, whereinthe first insulation layer or the second insulation layer having thelow-k (low dielectric constant) consists of one of a Si—O basedinorganic polymer, a carbon-based organic polymer, a fluorine-dopedoxide layer, and a carbon-doped oxide layer.
 5. The semiconductor deviceof claim 4, wherein the organic polymer consists of at least one of apolyally ether resin, a cyclic fluorine resin, a siloxane copolymer, afluoro polyally ether resin, a poly pentafluoride styrene resin, a polytetrafluoride styrene resin, a fluoro polyimide resin, a fluoro polynaphthalene resin, and a polycide resin.
 6. The semiconductor device ofclaim 1, wherein the etch stop layer is formed to a thickness of 5 to 30nm.
 7. The semiconductor device of claim 1, wherein the conductivematerials simultaneously fill the inter-connection groove and the viahole by using a CMP process.
 8. A method of forming a metal line in asemiconductor device, comprising: forming a first insulation layer and afirst etch stop layer on a conductive layer, and forming a firstphotosensitive layer pattern on the first etch stop layer; forming afirst opening for a via hole by etching the first etch stop layer usingthe first photosensitive layer pattern as a mask; forming a secondinsulation layer and a second etch stop layer on the first insulationlayer and the first etch stop layer, and forming a second photosensitivelayer pattern on the second etch stop layer; forming a second openingfor an inter-connection groove by etching the second etch stop layerusing the second photosensitive layer pattern as a mask; simultaneouslyforming the inter-connection groove and the via hole by etching thefirst insulation layer and the second insulation layer using the secondetch stop layer and the first etch stop layer as a mask; and forming ametal line by filling the inter-connection groove and the via hole withconductive materials.
 9. The method of claim 8, wherein the firstinsulation layer or the second insulation layer has a low-k (lowdielectric constant).
 10. The method of claim 9, wherein the firstinsulation layer or the second insulation layer having the low-k (lowdielectric constant) consists of one of a Si—O based inorganic polymer,a carbon-based organic polymer, a fluorine-doped oxide layer, and acarbon-doped oxide layer.
 11. The method of claim 8, wherein the firstopening is formed more widely than a predetermined width of the viahole, or the second opening is formed more widely than a predeterminedwidth of the inter-connection groove.
 12. The method of claim 8, whereinthe first etch stop layer or the second etch stop layer is formed to athickness of 5 to 30 nm.
 13. The method of claim 8, wherein the etchingfor the first insulation layer in the forming of the inter-connectiongroove and the via hole is performed by etching a portion of the entirethickness of the first insulation layer.
 14. The method of claim 8,wherein the etching for the first insulation in the forming of theinter-connection groove and the via hole is performed so as to penetratethe first insulation layer.
 15. The method of claim 13, wherein, afterthe forming of the inter-connection groove and the via hole, a spacer isformed on an entire surface of the substrate including theinter-connection groove and the via hole.
 16. The method of claim 8,wherein the first etch stop layer, the second etch stop layer, and thespacer insulation layer are composed of materials having the same etchselectivity.
 17. The method of claim 15, wherein the first etch stoplayer, the second etch stop layer, and the spacer insulation layer arecomposed of materials having the same etch selectivity.
 18. The methodof claim 16, wherein the first etch stop layer, the second etch stoplayer, and the spacer insulation layer are composed of silicon nitride.19. The method of claim 17, wherein the first etch stop layer, thesecond etch stop layer, and the spacer insulation layer are composed ofsilicon nitride.
 20. The method of claim 15, wherein widths of theinter-connection groove and the via hole are adjusted by controlling aforming thickness of the spacer insulation layer.
 21. The method ofclaim 20, wherein the width of the via hole connected to the conductivelayer is determined by additionally etching the first insulation layerup to the conductive layer in order to correspond to the adjusted widthof the via hole.
 22. A method of forming a metal line in a semiconductordevice, comprising: sequentially forming a first etch stop layer, afirst insulation layer, and a second etch stop layer on a conductivelayer; forming a first photosensitive layer pattern having a firstopening on the second etch stop layer; etching the second etch stoplayer by using the first photosensitive layer pattern as a mask to adegree that the first insulation layer is exposed, and then removing thefirst photosensitive layer pattern; sequentially forming a secondinsulation layer and a third etch stop layer on the first insulationlayer and the second etch stop layer, and forming a secondphotosensitive layer pattern having a second opening on the third etchstop layer; etching the third etch stop layer by using the secondphotosensitive layer pattern as a mask to a degree that the secondinsulation layer is exposed, and removing the second photosensitivelayer pattern; forming an inter-connection groove and a via hole bysequentially etching the first insulation layer using the third etchstop layer and the second etch stop layer as a mask; forming a spacerinsulation layer on an entire surface of a substrate including theinter-connection groove and the via hole; forming a spacer at bothsidewalls of the inter-connection groove and the via hole by performingan etch back process using the thickness of the spacer insulation layeras a target; forming a via hole by additionally etching the firstinsulation layer to a degree that the first etch stop layer is exposed;simultaneously forming the inter-connection groove and the via hole byremoving the first etch stop layer, the second etch stop layer, thethird etch stop layer, and the spacer insulation layer; and forming ametal line by performing a CMP process for polishing conductivematerials which fill in the inter-connection groove and the via hole.23. The method of claim 22, wherein the first insulation layer or thesecond insulation layer is composed of an organic polymer having a low-k(low dielectric constant).
 24. The method of claim 22, wherein the firstinsulation layer or the second insulation layer having the low-k (lowdielectric constant) consists of one of a Si—O based inorganic polymer,a carbon-based organic polymer, a fluorine-doped oxide layer, and acarbon-doped oxide layer.
 25. The method of claim 22, wherein, duringthe forming of the first photosensitive layer pattern and the secondphotosensitive layer pattern, the first insulation layer and the secondinsulation layer are protected by the second etch stop layer and thethird etch stop layer in a rework process to remove the firstphotosensitive layer pattern or the second photosensitive layer patternfor performing an additional lithography process.
 26. The method ofclaim 22, wherein the inter-connection groove and the via hole aresimultaneously formed by performing etching with the use of the thirdetch stop layer pattern as a mask.
 27. The method of claim 22, whereinthe inter-connection groove and via hole having a finer size than a sizelimit obtained by a lithography process are formed by adjusting athickness of the spacer.
 28. The method of claim 22, wherein, before theconductive materials fill the inter-connection groove and the via hole,a barrier metal layer is formed at both sidewalls thereof.
 29. Themethod of claim 28, wherein the barrier metal layer consists of at leastone of Ta, TaN, TiN, WN, TaC, WC, TiSiN, and TaSiN.